1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly, to a free wheel diode having field limiting layer, used as an intelligent power module.
2. Description of the Background Art
Free wheel diodes (hereinafter referred to as "FWD") have been conventionally used as an intelligent power module. The operation of such an FWD 200 in a half bridge circuit 400 as shown in FIG. 27 for simulation evaluation of the FWD will be described by way of illustration. The on/off of the half bridge circuit is controlled by an Insulated Gate Bipolar Transistor (hereinafter referred to as "IGBT") 210. When a waveform as shown in FIG. 28 for example is transmitted from a power supply to IGBT 210, IGBT 210 turns on from an off state. At this time, the waveforms of current and voltage between nodes 0 and 1 and the waveforms of current and voltage between nodes 1 and 2 are as shown in FIGS. 29 and 30, respectively. When IGBT 210 is off, a forward bias is applied to FWD 200, while when IGBT 210 is on, a reverse bias is applied to FWD 200. When the turning on completes, FWD 200 continues to be provided with a high reverse bias voltage.
The internal state of FWD 200 when the high reverse bias voltage is applied will be described by referring to FIGS. 16 to 26. FIG. 16 is a plan view of a conventional FWD, and a cross section thereof taken along line x--x is given in FIG. 17. The structure of the conventional FWD will be now described by referring to FIGS. 16 and 17.
The conventional FWD has an anode layer 103 provided in the center of a main surface of a semiconductor substrate 101 in the surface of the semiconductor substrate viewed from the side of an anode electrode. A field limiting innermost circumferential layer 104 is provided around anode layer 103. A plurality of annular field limiting layers 105 at prescribed distances outwardly from and surrounding field limiting innermost circumferential layer 104 are formed such that annular field limiting layers 105 gradually increase their sizes outwardly. A stopper channel 106 is provided at the utmost circumference of semiconductor substrate 101.
As shown in FIG. 17, in the cross section taken along line x--x in FIG. 16, n-type semiconductor substrate 101 having a width w.sub.2 of 5600 .mu.cm and a thickness t of 500 .mu.m includes a cathode layer 102, an n-type impurity diffusion region formed from the bottom side of semiconductor substrate 101 to a prescribed thickness and having a concentration higher than semiconductor substrate 101, and an anode layer 103, p-type impurity diffusion region having a surface concentration of 5.times.10.sup.16 /cm.sup.3 and width w.sub.3 of 3450 .mu.m and formed from about the center of the main surface on the top side of semiconductor substrate 101 to a position at a prescribed distance and at the diffusion depth of 6 .mu.m from the main surface on the top side.
There is formed, on the main surface on the top side of semiconductor substrate 101, a field limiting innermost circumferential layer 104, an annular p-type impurity diffusion region two-dimensionally surrounding anode layer 103, formed deeper than anode layer 103, and having a diffusion depth of 10 .mu.m from the main surface on the top side, a diffusion concentration of 1.times.10.sup.19 /cm .sup.3 higher than anode layer 103, and a width w.sub.4 of 50 .mu.m. A plurality of field limiting layers 105, a group of annular p-type impurity diffusion regions when viewed two-dimensionally, formed at prescribed distances outwardly from field limiting innermost circumferential layer 104 and having the same concentration as field limiting innermost circumferential layer 104. A stopper channel layer 106, an n-type impurity diffusion region having a concentration higher than semiconductor substrate 101 is provided at the outermost circumference of semiconductor substrate 101.
There are provided a metal layer 107 for cathode electrode (hereinafter cathode electrode metal layer 107) composed of gold (Au) or the like, adjacent to cathode layer 102, and a metal layer 108 for anode electrode (hereinafter anode electrode metal layer 108) composed of aluminum, adjacent to anode layer 103 and having a width w.sub.1 of 3450 .mu.m.
A forward bias is applied to this FWD if IGBT 210 serving as a switch in half bridge circuit 400 is off, and therefore a positive potential is applied to anode electrode metal layer 108, and a negative potential is applied to cathode electrode metal layer 107. Thus, in the cross section taken along D--D in FIG. 17, a current passed from anode layer 103 toward cathode layer 102, and a current passed from p-type anode layer 103 to cathode layer 102 via field limiting innermost circumferential layer 104 are generated. The current density distribution and the positive hole density distribution inside the device at this time are given in FIGS. 19 and 20, respectively. When a reverse bias is applied, in other words, a positive potential in view of the potential of anode electrode metal layer 108 as a reference potential is applied to cathode metal layer 107, the equipotential surface gradually extends from one field limiting layer 105 to another gradually outwardly from field limiting innermost circumferential layer 104 as the potential increases and electric field concentration in the vicinity of the surface of semiconductor substrate 101 may be relaxed.
At this time, as can be seen from the current density distribution in FIG. 19, a region having a higher current density than its periphery appears from 3.times.10.sup.3 .mu.m to 4.times.10.sup.3 .mu.m in the abscissa representing distance x from line B--B in the plan view of the FWD in FIG. 17, in other words, at the bottom side portion of field limiting innermost circumferential layer 104. This is because p-type field limiting innermost circumferential layer 104 having a high density is provided at the position at a distance in the range from 3.times.10.sup.3 .mu.m to 4.times.10.sup.3 .mu.m from line B--B in FIG. 17 as shown in FIG. 20, and the hole density is large as a result. The resistance value of n-type semiconductor substrate 101 at the bottom side part of field limiting innermost circumferential layer 104 is thus reduced, which more easily allows a current therethrough.
Field limiting innermost circumferential layer 104 is provided for preventing the concentration of electric field at the outermost circumferential part of anode layer 103 when a reverse bias is applied, and as shown in FIGS. 21 and 22, the larger the radius of curvature of an end of field limiting innermost circumferential layer 104, the larger will be the distribution of charges along the circumference, so that the concentration of electric field is less likely. In order to increase the radius of curvature of field limiting innermost circumferential layer 104, an impurity must be implanted from the main surface of semiconductor substrate 101 to a position deeper than anode layer 103 as shown in FIG. 23. Furthermore, in order to shorten time required for the step of diffusing the impurity, the concentration of impurity to be implanted is sometimes increased, or the impurity is sometimes implanted such that the width w.sub.5 of a region overlapping anode layer 103 is large as shown in FIG. 24 rather than small width w.sub.5 as shown in FIG. 23. If the radius of curvature of the pn junction between field limiting innermost circumferential layer 104 and semiconductor substrate 101 is small, interspaces 111 between the equipotential surfaces are narrow and electric fields concentrate therearound. As a result, as shown in FIG. 26, an impurity must be implanted perpendicularly to the surface of semiconductor substrate 101 over a wide range, in order to increase the radius of curvature of the pn junction plane between field limiting innermost circumferential layer 104 and semiconductor substrate 101, and interspaces112 between equipotential surfaces should be increased. Hence, the concentration of the impurity in field limiting innermost circumferential layer 104 is considerably larger than that of anode layer 103.
FWD 200 is however switched from the state with a forward bias to the state with a reverse bias when IGBT 210 serving as a switch for the half bridge circuit is switched from an off state to an on state. At this time, a negative potential is applied to anode layer 103 in view of the potential of cathode electrode 102 as a reference potential, and the holes having position charges passed from the side of anode layer 103 to the side of cathode layer 102 in semiconductor substrate 101 are flowed back toward anode layer 103. At this time, the current from the bottom side of field limiting innermost circumferential layer 104 toward cathode layer 102 is flowed back toward anode layer 103 and field limiting innermost circumferential layer 104. At this time, a recovery current passed from the inside of semiconductor substrate 101 toward field limiting innermost circumferential layer 104 is flowed back locally in a great density. As a result, the temperature rises in the vicinity of field limiting innermost circumferential layer 104, and field limiting innermost circumferential layer 104 could be destroyed.